Packages with stacked dies and methods of forming the same

ABSTRACT

A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a continuation of U.S. patent application Ser. No. 15/989,953, entitled “Packages with Stacked Dies and Methods of Forming the Same,” filed on May 25, 2018, which is a continuation of U.S. patent application Ser. No. 15/147,574, entitled “Packages with Stacked Dies and Methods of Forming the Same,” filed on May 5, 2016, now U.S. Pat. No. 9,984,999 issued May 29, 2018, which is a divisional of U.S. patent application Ser. No. 14/166,399, entitled “Packages with Stacked Dies and Methods of Forming the Same,” filed on Jan. 28, 2014, now U.S. Pat. No. 9,343,433 issued May 17, 2016, which applications are incorporated herein by reference.

BACKGROUND

Stacked dies are commonly used in Three-Dimensional (3-D) integrated circuits. Through the stacking of dies, the footprint of packages is reduced. In addition, the metal line routing in the dies is significantly simplified through the formation of stacked dies.

In some applications, a plurality of stacked dies is stacked to form a die stack. The total count of the stacked dies may sometimes reach eight or more. When such a die stack is formed, a first die is first bonded onto a package substrate through flip-chip bonding, wherein solder regions/balls are reflowed to join the first die to the package substrate. A first underfill is dispensed into the gap between the first die and the package substrate. The first underfill is then cured. A test is then performed to ensure that the first die is connected to the package substrate correctly, and the first die and the package substrate function as desired.

Next, a second die is bonded onto the first die through flip-chip bonding, wherein solder regions/balls are reflowed to join the second die to the first die. A second underfill is dispensed into the gap between the second die and the first die. The second underfill is then cured. A test is then performed to ensure that the second die is connected to the first die and the package substrate correctly, and the first die, the second die, and the package substrate function as desired. Next, a third die is bonded onto the second die through the same process steps as for bonding the first die and the second die. The processes are repeated until all the dies are bonded.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1 through 7 illustrate the cross-sectional views of intermediate stages in the formation of a die stack in accordance with some embodiments;

FIG. 8A illustrates a cross-sectional view of a die stack in accordance with some embodiments;

FIG. 8B illustrates a top view of a die stack in accordance with some embodiments;

FIGS. 9 through 13 illustrate the cross-sectional views of intermediate stages in the formation of a package in accordance with some embodiments; and

FIG. 14 illustrates a cross-sectional view of a package in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

An integrated circuit package and the method of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages of forming the package are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

Referring to FIG. 1 , wafer 100 is provided. Wafer 100 includes a plurality of device dies 102, which have circuits identical to each other. In some embodiments, wafer 100 is a memory wafer, and device dies 102 are memory device dies, which may be Static Random Access Memory (SRAM) device dies, Dynamic Random Access Memory (DRAM) device dies, Magneto-resistive Random Access Memory (MRAM) device dies, or the like. In alternative embodiments, device dies 102 are logic device dies that include logic circuits such as mobile application circuits, for example.

Device dies 102 includes semiconductor substrate 104, wherein the active devices (not shown) such as transistors are formed at a surface of semiconductor substrate 104. In some embodiments, semiconductor substrate 104 is a crystalline silicon substrate. In alternative embodiments, semiconductor substrate 104 includes another semiconductor material such as germanium, silicon germanium, a III-V compound semiconductor material, or the like. Metal lines and vias (not shown) are formed in the interconnect structures of device dies 102 to interconnect the integrated circuit devices in device dies 102.

Through-vias (sometimes referred to as Through-Silicon Vias (TSVs) or through-semiconductor vias) 106 are formed to penetrate through semiconductor substrate 104. Additional electrical connectors (such as metal pads, metal pillars, or metal pillars/pads and the overlying solder layers) 108 are formed on the top surfaces of device dies 102. Electrical connectors 110 are formed at the bottom surfaces of device dies 102. Electrical connectors 108 and 110 may be metal pads, metal pillars, or the like. Electrical connectors 108 are electrically coupled to electrical connectors 110 through through-vias 106. In some embodiments, solder balls 111 are attached to electrical connectors 110. In alternative embodiments, no solder balls are attached to electrical connectors 110.

Next, referring to FIG. 2 , device dies 202 are bonded to device dies 102 through flip-chip bonding. The respective bonding process is referred to as a chip-on-wafer bonding. In accordance with some embodiments of the present disclosure, device dies 202 are memory device dies, which may include SRAM device dies, DRAM device dies, MRAM device dies, or the like. In alternative embodiments, device dies 202 are logic device dies that include logic circuits such as mobile application circuits, for example. In some embodiments, the circuits in device dies 202 are identical to those of device dies 102. In alternative embodiments, the circuits in device dies 102 and device dies 202 are different from each other.

Each of device dies 202 includes semiconductor substrate 204, wherein the active devices (not shown) such as transistors are formed at a surface of semiconductor substrate 204. In some embodiments, semiconductor substrate 204 is a crystalline silicon substrate. In alternative embodiments, semiconductor substrate 204 includes another semiconductor material such as germanium, silicon germanium, a III-V compound semiconductor material, or the like. Metal lines and vias (not shown) are formed in the interconnect structures of device dies 202 to interconnect the integrated circuit devices in device dies 202.

Through-vias 206 are formed to penetrate through semiconductor substrate 204. Additional electrical connectors 208 are formed on the top surfaces of device dies 102. Electrical connectors 210 are formed at the bottom surfaces of device dies 202. Electrical connectors 208 and 210 may be metal pads, metal pillars, or the like. Electrical connectors 208 are electrically coupled to electrical connectors 210 through through-vias 106. Furthermore, the integrated circuits in device dies 202 and electrical connectors 208 are electrically connected to electrical connectors 110 in device dies 102.

FIG. 3 illustrates the dispensing and the curing of underfill 212. In some embodiments, underfill 212 is dispensed into the gaps between device dies 102 and the respective overlying device dies 202. The gaps between neighboring device dies 202 are not dispensed with underfill 212. Underfill 212 is then cured, for example, in a thermal curing process. The curing may be performed at a temperature in the range between about 100° C. and about 165° C., for example, for a period of time in the range between about 30 minutes and about 120 minutes. After the curing, underfill 212 is solidified.

FIGS. 4 and 5 illustrate the bonding of device dies 302 and the dispensing of underfilling material 312, which may be an underfill, a Non-Conductive Paste (NCP), or a Non-Conductive Film (NCF) 312. Referring to FIG. 4 , device dies 302 are bonded to device dies 202 with a one-to-one correspondence. In some embodiments, device dies 302 are identical to device dies 202. In these embodiments, device dies 202 and 302 may be formed using identical process steps, wherein the different reference numerals 202 and 302 are merely used to indicate that they are at different levels in the die stacks. In alternative embodiments, device dies 202 and 302 have different structures including different circuits and/or different metal routing, etc.

Next, as shown in FIG. 5 , underfilling material 312 is dispensed and cured. In some embodiments, underfilling material 312 is dispensed into the gaps between device dies 202 and the respective overlying device dies 302. The gaps between neighboring device dies 302 are not dispensed with underfilling material 312. Underfilling material 312 is then cured, for example, in a thermal curing process. The curing may be performed using same conditions as curing underfill 212. For example, the curing may be performed at a temperature in the range between about 100° C. and about 165° C., and for a period of time in the range between about 30 minutes and about 120 minutes. After the curing, underfilling material 312 is solidified.

FIG. 6 illustrates the bonding of device dies 402 and the dispensing of underfilling material 412, which may be an underfill, a NCP, or an NCF. Device dies 402 are bonded to device dies 302 with a one-to-one correspondence. Again, device dies 402 may be identical to, or may be different from, device dies 302 and/or 202. The dispensing and the curing of underfilling material 412 may be the same as the dispensing and the curing of underfilling material 312.

Next, FIG. 7 illustrates the bonding of device dies 502 and the dispensing of underfilling material 512. Device dies 502 are bonded to device dies 402 with a one-to-one correspondence. Again, device dies 502 may be identical to, or may be different from, device dies 402, 302, and/or 202. The dispensing and the curing of underfilling material 512 may be the same as the dispensing and the curing of underfilling material 412.

Although not illustrated, additional device dies may be bonded over device dies 502 to increase the stacking level. Each of the additional device dies may be identical to, or may be different from, device dies 502, 402, 302, and/or 202.

Also referring to FIG. 7 , a die-saw is performed along scribe line 114 in wafer 100, resulting in a plurality of die stacks 10, as illustrated in FIGS. 8A and 8B. Each of die stacks 10 includes device dies 102, 202, 302, 402, 502, and possible more device dies. In alternative embodiments, each of die stacks 10 includes fewer device dies such as two, three, or four device dies. For example, each of die stacks 10 may include only two device dies 102 and 202.

FIGS. 8A and 8B illustrate a cross-sectional view and a top view, respectively, of die stack 10. As shown in FIG. 8B, die stack 10 includes device die 102, on which one or a plurality of device dies such as 202, 302, 402, and 502 are bonded. Device die 102 has a top-view area greater than the top-view areas of the overlying device dies 202, 302, 402, and 502. This is because device die 102 is sawed from wafer 100 (FIG. 7 ) after the bonding of device dies, and hence a margin width W1 is left between the edges of device dies 102 and the respective edges of device dies 202/302/402/502, so that during the die-saw, device dies 202/302/402/502 are not damaged by the sawing blade. In accordance with some embodiments, margin width W1 is greater than about 10 μm, and may be in the range between about 10 μm and about 100 μm.

The device dies overlying device die 102, such as device dies 202, 302, 402, and 502, may have identical structures. For example, not only their internal circuits are the same, their sizes are also the same. For another example, device dies 202, 302, 402, and 502 may have a same top-view area, with the respective edges of device dies 202, 302, 402, and 502 aligned, as illustrated in FIGS. 8A and 8B. The respective electrical connectors of device dies 202, 302, 402, and 502 may also be aligned. Device die 102 may have a top-view area greater than the top-view areas of device dies 202, 302, 402, and 502, although device die 102 may have a same structure (except the top view size) and same circuits as device dies 202, 302, 402, and 502. For example, device dies 202, 302, 402, and/or 502 may be sawed from the wafers that are identical to wafer 100 (FIG. 1 ).

FIG. 9 illustrates a cross-sectional view of package substrate 12. In some exemplary embodiments, package substrate 12 is a build-up substrate that is built up from core 24. In alternative embodiments, package substrate 12 is a laminate (or build-up) substrate that includes conductive traces embedded in laminated dielectric films. In the subsequent discussion of the embodiments of the present disclosure, a build-up substrate is illustrated as an example, while the teaching revealed in accordance with the exemplary embodiments are readily applicable to laminate substrates.

The exemplary package substrate 12 in accordance with various embodiments of the present disclosure may include top electrical connectors 30, bottom electrical connectors 32, and the intermediate metal traces, vias, and the like connecting top electrical connectors 30 to bottom electrical connectors 32. Core 24 includes dielectric layer 25, and conductive pipes 26 penetrating through dielectric layer 25. Dielectric layer 25 may be formed of fiber glass or other dielectric materials.

Next, referring to FIG. 10 , device die 34 is bonded to package substrate 12. In some embodiments, the bonding is through solder bonding, wherein solder regions 36 bond device die 34 and package substrate 12 together. In alternative embodiments, the bonding is through metal-to-metal (for example, copper-to-copper) direct bonding. Device die 34 may be a logic die, which may further be a Central Processing Unit (CPU), a Graphic Processing Unit (GPU), or the like.

Device die 34 includes semiconductor substrate 38, wherein the active devices (not shown) such as transistors are formed at a surface of semiconductor substrate 38. Through-vias 40 are formed to penetrate through semiconductor substrate 38. Additional electrical connectors 42 are formed on the top surface of device die 34. Electrical connectors 44 are formed at the bottom surface of device die 34. Electrical connectors 42 and 44 may be metal pads, metal pillars, or the like. Electrical connectors 42 are electrically coupled to electrical connectors 36 and electrical connectors 44 through through-vias 40.

Next, as shown in FIG. 11 , underfill 46 is dispensed into the gap between device die 34 and package substrate 12, and is then cured, for example, in a thermal curing step. In alternative embodiments, instead of using underfill, a Non-Conductive Film (NCF) may be disposed between device die 34 and package substrate 12.

FIG. 12 illustrates the bonding of die stack 10 to device die 34. In some embodiments, as shown in FIG. 12 , device die 102 in die stack 10 is bonded to device die 34, and hence device die 502 becomes the top device die in the resulting package. In alternative embodiments, as shown in FIG. 14 , device die 502 is bonded to device die 34, and hence device die 102 becomes the top device die in the resulting package.

Referring back to FIG. 12 , after the bonding, an underfill 48 is dispensed and cured. In the resulting structure, the top device die, which may be device die 102 (FIG. 12 ) or 502 (FIG. 14 ) in the illustrated exemplary embodiments, are electrically connected to the underlying device die 34 and package substrate 12 through the electrical connections and through-vias in the intermediate device dies such as 202, 302, and 402.

FIG. 13 illustrates the attachment of metal lid 50, which is attached to the top surface of package substrate 12 through adhesive 52. In addition, Thermal Interface Material (TIM) 54 is applied, which is an adhesive having a high thermal conductivity. In some embodiments, TIM 54 has a thermal conductivity higher than about 1 W/m*K or higher. TIM 54 joins the top die (such as device die 502) in die stack 10 with metal lid 50, so that the heat generated in die stack 10 may be dissipated to metal lid 50. Metal lid 50 may also be attached to the top surface of device die 34 through TIM or adhesive 56. Metal lid 50 may be formed of copper, aluminum, stainless steel, or the like.

FIG. 14 illustrates a package in accordance with alternative embodiments of the present disclosure. These embodiments are similar to the embodiment in FIG. 13 , except that device die 102 is the top device die.

Various embodiments of the present disclosure have advantageous features. By stacking device dies 102, 202, 302, 402, 502, etc. to form a die stack, and then bonding the die stack to device die 34, elevated temperature applied in the formation of the die stack will not be applied on the respective package substrate 12 because the die stack is formed before it is bonded onto package substrate 12. Further, the warpage of package substrate 12 caused by the elevated temperature used for forming the die stack is reduced or eliminated. In addition, in some embodiments, the stacking of device dies 202, 302, 402, and 502 onto wafer 100 is achieved through a chip-on-wafer process, which has a higher throughput than stacking dies on discrete dies as in other approaches.

In accordance with some embodiments of the present disclosure, a method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

In accordance with alternative embodiments of the present disclosure, a method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. A third plurality of device dies is bonded onto the first plurality of device dies, with each of the third plurality of device dies bonded to one of the first plurality of device dies. The third plurality of device dies is identical to the first plurality of device dies. The wafer is sawed to form a plurality of die stacks, wherein each of the plurality of die stacks includes a first device die from the first plurality of device dies, a second device die from the second plurality of device dies, and a third device die from the third plurality of device dies. An additional device die is bonded onto a package substrate. After the bonding the additional device die onto the package substrate, one of the plurality of die stacks is bonded onto the additional device die.

In accordance with yet alternative embodiments of the present disclosure, a package includes a package substrate, a first device die over and bonded to the package substrate, and a die stack bonded to the first device die. The die stack includes a second device die over and bonded to the first device die, and a third device die over the second device die. The second device die and the third device die have identical integrated circuits, wherein a first top-view area of the second device die is different from a second top-view area of the third device die. The package is further bonded to a printed circuit board.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A package comprising: a die stack comprising: a first device die; a second device die over and bonded to the first device die, wherein the first device die extends laterally beyond respective edges of the second device die; a first underfill between the first device die and the second device die; a third device die over and bonded to the second device die, wherein edges of the third device die are flush with corresponding edges of the second device die; and a second underfill between the second device die and the third device die, wherein the first underfill and the second underfill are physically separated from each other; a metal lid comprising a top portion over the die stack, and a skirt portion on a side of the die stack, wherein the skirt portion is spaced apart from the die stack; and a thermal interface material between, and physically joined to, the die stack and the top portion of the metal lid.
 2. The package of claim 1, wherein the first underfill is limited in a first region between the first device die and the second device die, and the second underfill is limited in a second region between the second device die and the third device die.
 3. The package of claim 1, wherein no underfill is in a region higher than a bottom surface of the first device die, and lower than a top surface of the first device die.
 4. The package of claim 1 further comprising: a fourth device die underlying and bonding to the first device die, wherein the first device die, the second device die, and the third device die have identical circuits, and the fourth device die has circuits different from the identical circuits.
 5. The package of claim 4 further comprising: a package substrate underlying and bonding to the fourth device die.
 6. The package of claim 4, wherein all device dies in the die stack are memory dies that have identical memory circuits, and wherein the fourth device die is a logic device die.
 7. The package of claim 1, wherein edges of the first underfill and the second underfill are vertically aligned to edges of the second device die and the third device die.
 8. The package of claim 1, wherein the die stack further comprises a fourth device die over and bonding to the third device die, wherein the second device die, the third device die, and the fourth device die have identical integrated circuits.
 9. A package comprising: a die stack comprising: a plurality of first memory dies stacked together; and a second memory die underlying and bonded to the plurality of first memory dies, wherein the plurality of first memory dies and the second memory die have identical memory circuits, and each of the plurality of first memory dies has a first area smaller than a second area of the second memory die; a plurality of first underfills comprising portions extending into gaps that separate the plurality of first memory dies from each other; and a second underfill between the second memory die and a bottom die in the plurality of first memory dies, wherein each of the plurality of first underfills is physically separated from other ones of the plurality of first underfills, and is physically separated from the second underfill.
 10. The package of claim 9, wherein the plurality of first underfills have edges flush with corresponding edges of the plurality of first memory dies.
 11. The package of claim 10, wherein the second underfill extends laterally beyond the corresponding edges of the plurality of first memory dies.
 12. The package of claim 9 further comprising: a logic die underlying and bonded to the second memory die; and a package substrate underlying and bonded to the logic die.
 13. The package of claim 12 further comprising: a first adhesive over and contacting the logic die; and a metal lid having a first bottom surface contacting the first adhesive.
 14. The package of claim 13 further comprising: a second adhesive over and contacting the package substrate, wherein the metal lid further comprises a second bottom surface contacting the second adhesive.
 15. The package of claim 13, wherein the package substrate extends laterally beyond edges of the metal lid.
 16. A package comprising: a logic device die; a first memory die over and bonded to the logic device die; a first underfill between the first memory die and the logic device die; a second memory die over and bonded to the first memory die, wherein the first memory die and the second memory die have identical memory circuits, and the first memory die has a first top-view area greater than a second top-view area of the second memory die; a second underfill between the second memory die and the first memory die; wherein the first underfill laterally extends beyond corresponding edges of the second memory die, and the second underfill comprises edges flush with the corresponding edges of the second memory die; a third memory die over and bonded to the second memory die; a third underfill between the third memory die and the second memory die, wherein the second underfill and the third underfill are physically separated from each other; a first adhesive over and contacting the logic device die; and a metal lid contacting the first adhesive, wherein the metal lid further comprises a portion overlapping the third memory die.
 17. The package of claim 16 further comprising: a package substrate underlying and bonded to the logic device die; and a second adhesive over and contacting the package substrate, wherein the metal lid is further joined to the second adhesive.
 18. The package of claim 16, wherein the third memory die also has the identical memory circuits.
 19. The package of claim 4, wherein the skirt portion comprises an inner portion overlapping the fourth device die, and an outer portion extending laterally beyond edges of the fourth device die.
 20. The package of claim 4, wherein the skirt portion comprises a first bottom surface higher than the fourth device die, and a second bottom surface lower than the fourth device die. 